1. Field of the Invention
The present invention relates to electrical circuits and more particularly to an integrated circuit protection circuit which prevents damage to an integrated circuit due to transient surges or electrostatic discharges and which clears the integrated circuit of a "latch up" condition or SCR mode.
2. Description of the Prior Art
In the fabrication of integrated circuits, an epitaxial layer doped with one ion type (i.e. N-type of P-type) is grown on the surface of a substrate doped with the other ion type (i.e. P-type or N-type) and then various impurities are diffused into the epitaxial layer to create the requisite elements (e.g. the gate, channel, etc.) of the desired electronic device. The diffusion process, in addition to forming the desired electronic device, also can create what is well known in the art as a parasitic transistor which may exist between a diffusion region, the epitaxial layer and the substrate. When a CMOS inverter stage is formed a pair of parasitic transistors are formed which have the configuration of a silicon controlled rectifier (SCR) circuit. The parasitic transistors remain inactive during the normal operation of the integrated circuit and therefore generally do not have an effect on the operation of the integrated circuit. However, a transient surge or electrostatic discharge may change the relative electrical characteristics of one or more of the several diffusion regions enough so that the regions which comprise the parasitic SCR circuit become conductive and current passes through portions of the various layers of the integrated circuit unintended for such current flow. Such a phenomenon is referred to as a "latch up" condition or SCR mode (hereinafter referred to as a "latch up" condition). The "latch up" condition can be especially destructive to CMOS integrated circuits, since they and their associated components are designed to normally draw small quantities of current. An integrated circuit may be cleared of the "latch up" condition by reducing the input voltage or current below the sustaining voltage or sustaining current, respectively, the value of which may vary according to the integrated circuit being used. A more detailed description of "latchup" may be found in RCA CMOS DATA BOOK, Integrated Circuit Application Note (ICAN) 6525.
When a "latch up" condition occurs, the integrated circuit appears as a very low impedance across the output of a voltage regulator which may be used to drive the integrated circuit. Thus, it not only becomes necessary to limit the current input to the integrated circuit for protection, but also to clear the integrated circuit of the "latch up" condition so that the integrated circuit may again function properly.
The present invention provides such a device which not only monitors the operation of the integrated circuit, but also drops the input current and/or input voltage below the sustaining current or sustaining voltage, respectively, of the integrated circuit for some predetermined time, thereby clearing the integrated circuit of the "latch up" condition.